Intellectual Ventures I LLC, et al. v. Toshiba Corporation, et al., C.A. No. 13-453- SLR, December 17, 2015.

Robinson, J.  .  Claim construction opinion issues regarding twenty-six terms from eight patents.

The disputed technology relates to computer memory. The following terms were considered:

1. “First and second banks of memory”
2. “Plurality of memory banks”
3. “Redundant memory cells”
4. “Allowing said processing circuitry to address at least one of said primary [redundant] memory cells”
5. “Redundancy bus”
6. “Redundancy cell memory space spate form said primary cell memory space”
7. “A plurality of array of memory cells”
8. “A plurality of registers”
9. “Data transfer circuitry for transferring parallel bits of data from any selected one of said arrays through the corresponding said register to any other selected one of said arrays through the corresponding said register”
10. “Substantially simultaneously inputting said row address bit and column address bit”
11. “Column address”
12. “Command and control cycle”
13. “Addresses”
14. “Receiving addresses”
15. “Sensing the bitlines of the array to read data stored in the cells of the selected row with a bank of master sense amplifiers”
16. “Writing the data”
17. “Systems operation signals during the normal system operation”
18. “System operation signals on said system bus during normal system operation”
19. “System bus”
20. “Bus interrupt line”
21. “Data transfer speed of the peripheral device”
22. “Locate peripheral client sequence”
23. “Packet-to-ATA bridge”
24. “Packet-to-ATA bridging device”
25. “Parsing the command block into a sequence of ATA register operation:
26. “ATA interface”